Mentor Graphics Corp. (NASDAQ: MENT), the market and technology leader in high-level synthesis solutions, today announced that the Catapult^® C Synthesis tool has been extended to support control logic and manage low power design requirements, thus enabling full-chip high-level synthesis (HLS). This breakthrough technology allows designers to use pure ANSI C++ for both algorithmic blocks and control logic blocks. Extending the Catapult C tool’s capabilities to full-chip high-level synthesis is critical due to the rapid growth in design size and complexity, which requires engineers to design hardware functionality at higher levels of abstraction.

Control logic synthesis and algorithmic synthesis have traditionally been addressed using different languages, formalisms and abstractions. The latest advances in the Catapult C Synthesis tool unifies these two domains, allowing users to describe control logic along with algorithmic behavior in a single and coherent model leveraging standard ANSI C++. At the heart of this innovation is a new synthesizable C++ construct, which allows designers to easily specify asynchronous data communication, allowing full control over concurrent hardware creation. This pivotal mechanism allows interfacing algorithmic representations driven by the dataflow with control-dominated blocks synchronized by clocks. The result is a coding style familiar to hardware designers, letting users easily express communication, priority and task coordination within an abstract representation of concurrency. The new approach formalizes a modeling style, which provides the necessary accuracy for control oriented tasks, while preserving the abstraction beneficial for algorithmic subsystems.

The synthesis process is complemented by a patent-pending and fully automated verification flow which for the first time lets users validate the detailed RTL-level block interactions at the C level. Tight integration between verification and synthesis has proved a necessity to realizing the full potential of HLS. A common pitfall found with other HLS tools is developing high-level synthesis in isolation, which results in overly complex verification of the RTL output.

"Our digital broadcasting ICs typically consist of a complex mix of compute intensive algorithmic units and control dominated blocks," said Professor Schlicht, Head of Department, Fraunhofer Institute for Integrated Circuits. "The new Catapult extensions for control-logic synthesis provide us with the capability to develop an increasing portion of the overall system using high-level synthesis from C++.