Hitachi's Deployment of Allegro Global Route Environment Technology Significantly Streamlines PCB Design Process

SAN JOSE, CA -- (Marketwire) -- 06/30/09 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that the Cadence® Global Route Environment (GRE) technology for Cadence Allegro® PCB design enabled Hitachi, Ltd. to successfully reduce printed circuit board (PCB) place-and-route design time by 40% for a high-speed communication product. Hitachi applied the GRE place-and-route design methodology to its PCB place-and-route from interconnect planning to complete routing, with full constraints for high-speed digital signals where no automation was previously available. The time-saving results were reported by Hitachi Communication Technologies, Ltd., the communication products division of Hitachi Group, as part of a companywide initiative at Hitachi to enhance design efficiency and reduce design-cycle time.

"High-speed PCBs require significant enhancements in performance, and gigahertz-level signals are becoming common," said Toru Hiyama, general manager, MONOZUKURI Innovation Operation, Hardware MONOZUKURI Division at Hitachi. "Hitachi is always aiming at high-performance, high-quality products, and in order to complete the design in the shortest cycle time possible while maintaining high quality, it was critical for us to solve the bottleneck of place-and-route for PCBs. By using Cadence GRE technology, we can solve the routing bottleneck as well as enhance the reliability of the design."

The Cadence GRE technology is the next-generation interconnect planning and routing technology for PCB, and establishes a new PCB design paradigm. The GRE technology provides users with automation for various stages of interconnect planning and routing where no automation has been available. At the beginning of the process it allows users to plan the routing strategy at a high-level through Interconnect Flow Designer. Through the Interconnect Feasibility capability it checks and provides feedback on available space for each of the flows, allowing users to modify their routing strategy. In the middle of the planning process, it determines the overall routing feasibility, including the routing paths, net topologies and assigned electric constraints. In the final planning phase, the GRE technology performs feasibility routing against the pre-determined routing flow, and then automatically completes routing.