Jointly Developed with IBM, Supported by WISPA Consortium, RF Platform Builds on Enhanced Low-Power Process from Chartered

Chartered Semiconductor Manufacturing (Nasdaq:CHRT) (SGX:CHARTEREDSC), one of the world’s top dedicated foundries, today announced a robust 65-nanometer (nm) RF platform specifically geared for developers of single-chip RF products. The Chartered process offering, jointly developed with IBM, is based on Chartered’s enhanced 65nm low-power process (65nm LPe), and includes an IBM RF physical design kit (PDK) available from Chartered. This RF Platform comes with broad RF design enablement from leading analog IP suppliers and the Wireless SoC Platform Alliance (WISPA) consortium.

The RF platform is supported by an RF PDK specifically for the 65nm LPe process. The kit significantly reduces design time and helps ensure first-time-right silicon for full-featured SoCs with integrated RF. It has been characterized and silicon-validated on the process on Chartered-manufactured silicon, and uses proven techniques from IBM to achieve a high degree of model-to-silicon accuracy. The PDK enables a more flexible methodology, based on a unique parameterized cell (p-cell) design approach that allows designers to tune RF components in a wide variety of ways.

The comprehensive PDK consists of a full palette of transistors and passives, including high fT RF transistors, vertical native (VNCAPs) and MIM capacitors, large tuning range MOS varactors, high Q-factor shielded inductor, precision poly resistors, and RF ESD devices. These device solutions are complemented by RF-centric p-cells, an inductor synthesis kit, EM simulators setup files support and substrate noise analysis kit.

Single-Chip RF Solution

As consumer multi-media mobile applications continue to expand in features and functionality, integrated high-speed wired and wireless connectivity have become essential. Combining high-speed wired and RF subsystems on a single SoC has been a challenge for most companies, historically forcing them to use the less favorable option of multiple-chip solutions that compromise cost and end-product form factor.