NITROX DPI CN17xx Family Uses Cavium's Innovative 3rd Generation Deep Packet Inspection Technology; Delivers 4 to 20 Gbps Performance Independent of Pattern Rule-Set Size, With Support for Very Large Number of Patterns for Future-Proofing Designs

MOUNTAIN VIEW, CA -- (Marketwire) -- 07/20/09 -- Cavium Networks (NASDAQ: CAVM), a leading provider of highly integrated semiconductor products that enable intelligent processing for networking, storage, wireless and video applications, today announced the NITROX DPI CN17XX Layer 7 Content Processor Family. The NITROX DPI CN17XX processors offer 4 Gbps to 20 Gbps of deterministic performance with low latency and support for an unlimited number of pattern rule-sets and flows. The NITROX DPI processors target a wide range of applications including application level firewalls, intrusion prevention (IPS), gateway anti-virus, unified threat management and content-based QoS in routers, switches, appliances and services blades for the Enterprise, Datacenter and Service Provider markets. This scalable product family is offered to customers as silicon products as well as production-ready boards with extensive software support.

Two trends in the networking marketplace are driving the need for L7 content and deep packet inspection. Network security requirements have now evolved to include IPS, Anti-Virus, Malware, Spam and DoS in addition to the traditional VPN, Firewall and IDS functionality. Additionally, with the rapid integration of voice, video and data traffic on the network, content-based QoS is critical. Networking equipment built to address these evolving content processing needs must address several challenges in order to meet increasing line rate performance. The performance has to be deterministic with low latency to support increasing multi-media and real-time traffic. Additionally, performance has to be independent of the number of pattern rule-sets and flows as the number of content inspection signatures and traffic flows is increasing rapidly. Finally, solution scalability and flexibility is required to address several price/performance points and different system architectures.

Solutions available in the marketplace today often fall short in addressing these requirements. Some solutions limit the number of flows while others deliver acceptable performance only for a limited pattern rule-set which fits in on-chip memory.