Mentor Graphics Corporation (NASDAQ: MENT) today announced that it has expanded the set of Mentor tools and technologies included in TSMC Reference Flow 10.0. The expanded Mentor® track supports advanced functional verification for complex ICs, netlist-to-GDSII implementation for 28nm ICs, tighter integration with the ubiquitous Calibre® physical verification and DFM platform, and tools for layout aware test failure diagnosis. In addition, this newly introduced Mentor track also addresses low power design with Mentor tools for functional verification, IC implementation and IC testing.

“Mentor Graphics continues to expand its Reference Flow offerings to cover the total IC design cycle from the systems level through functional verification, place-and-route, physical verification and silicon test, as well as offering new solutions such as low power, manufacturing variability, and silicon yield analysis,” said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC.

The Reference Flow 10.0 Mentor track provides new capabilities in many areas, including the first Mentor implementation solution in TSMC Reference Flow, the Olympus-SoC™ place-and-route system.