Second Generation PCIe FPGA Block Achieves PCI-SIG 1-8 Lane Compliance with 50% Lower Power and 15% Higher Performance than Previously Available

SAN JOSE, Calif., July 27 /PRNewswire/ -- Xilinx (Nasdaq: XLNX) today announced that its newest generation Virtex(R)-6 FPGA family is compliant with the PCI Express(R) 2.0 specification, delivering up to 50 percent lower power than previous generations and 15 percent higher performance than competitive offerings. The second-generation PCIe(R) block integrated in Xilinx(R) Virtex-6 FPGAs has passed PCI-SIG PCI Express version 2.0 compliance and interoperability testing for 1 to 8-lane configurations, adding to the broad range of design resources from Xilinx and its alliance members that support the widely adopted serial interconnect standard. This significant industry milestone is expected to accelerate mainstream development of high bandwidth PCIe 2.0 systems for communications, multimedia, server and mobile platforms, enabling applications such as high definition video, high-end medical imaging, and industrial instrumentation among others.

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In addition, Xilinx has once again teamed up with key alliance members Northwest Logic Inc. and PLDA to provide Direct Memory Access (DMA) intellectual property (IP) cores for Virtex-6 FPGAs. This latest collaboration builds on their existing PCIe 2.0 soft IP for Virtex-5 FXT devices, the first FPGA to provide PCIe 2.0 x8-lane support with the Northwest Logic DMA core. DMA engines enable the efficient movement of data in systems, ensuring that the PCIe block in Virtex-6 FPGAs delivers maximum performance and bandwidth.

Designers can immediately begin the evaluation and design of PCI Express 2.0 compliant systems in Virtex-6 FPGAs. To assist in this effort, the Xilinx CORE Generator(TM) system delivered in the ISE(R) Design Suite provides the PCIe core, reference design and all the scripts, basic testbench, and simulation models needed to streamline integration into customer designs. Designers can download at no charge the ISE WebPACK(TM) software or trial version of the full featured ISE Design Suite from the Xilinx web site at: www.xilinx.com/tools/webpack.

"The demand for high-bandwidth connectivity is insatiable, and the PCIe 2.0 standard is critical to meeting the requirements of high performance, low power applications, especially in the telecommunications and server markets," said Tom Feist, senior marketing director for ISE Design Suite at Xilinx.