PowerMagic 65-Nanometer Design Methodology Leverages Cadence End-to-End CPF-Based Low-Power Solution

SAN JOSE, CA -- (Marketwire) -- 08/17/09 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that Global Unichip Corporation (GUC) has integrated the CPF-based Cadence Low-Power Solution into its PowerMagic™ methodology to optimize the design of its customers' complex low-power ASIC implementations in advanced technology.

GUC was able to develop a complete end-to-end low power ASIC flow, including dynamic voltage frequency scaling (DVFS) techniques, by integrating the Cadence® Low-Power Solution, including Cadence Encounter® RTL Compiler, Encounter Digital Implementation System and Encounter Conformal® Low Power, together with its proprietary in-house tools, into the PowerMagic methodology for design, verification, and implementation. These techniques are keys to enabling multiple power domains of variable voltages on a single chip and reducing voltage to circuits when peak performance is not required.

"Our designers benchmarked the capabilities of the Cadence Low-Power Solution by optimizing a 65-nanometer, 10-million-gate low power design while correctly implementing more than ten power domains and over 50 power modes," said C.C. Hsieh, vice president of Design Service at GUC. "Cadence low power solutions worked well in GUC's integrated PowerMagic methodology, which effectively resolved low power implementation and verification issues that puzzled ASIC designers in a complex low power design project."

The Cadence Low-Power Solution provides a complete methodology for design-to-signoff that begins with early design planning and includes front-end design, synthesis and physical implementation. It enables consistency and convergence through power estimation and analysis at every step. Alongside the implementation flow, comprehensive power verification is performed by leveraging static, dynamic and formal power verification techniques in a closed-loop verification methodology. This fully integrated, highly automated, power-aware solution is backed by industry-leading services capabilities and the industry's largest power-focused industry alliances -- the Power Forward Initiative and Si2's Low Power Coalition.

"By implementing the Cadence Low-Power Solution in its PowerMagic methodology for low-power design, GUC has delivered a tremendous productivity and quality boost to its design teams intent on providing superior low-power circuits to its customers," said Chi-Ping Hsu, senior vice president of digital implementation research and development at Cadence.