Oct. 15, 2009 (PR Newswire) --

SUNNYVALE, Calif., Oct. 15 /PRNewswire/ -- Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Anchor Bay, a leading supplier of video-processing semiconductors (ASICs) and systems, has successfully taped out its ABT2015 chip utilizing Denali's next-generation Databahn(TM) DDR PHY solution in 65-nanometer (nm) Common Platform(TM) process technology offered by IBM, Chartered Semiconductor Manufacturing Ltd., and Samsung Electronics Co., Ltd. Denali's Databahn solution enabled Anchor Bay's developers to meet optimal performance design requirements in their high-volume SoCs for video processing semiconductor products that advancing the optimum home theater experience.

"The superior quality produced by our advanced video processing algorithms places high demands on the performance of the DDR interface," said Satish Iyengar, Director, Semiconductor Engineering at Anchor Bay. "Denali's Databahn DDR synthesizable PHY was configurable, high-quality and delivered what no other vendor could within our time-to-market constraints. Denali's demonstrated the industry's best expertise and customer support and their PHY solution helped address our performance and design requirements."

Anchor Bay's ABT2015 chip is ideally suited for video processing functions in A/V receivers, Blu-ray player recorders, and digital displays. The chip includes all of Anchor Bay's award winning Video Reference Series(TM) technologies, including PReP(TM) (Progressive ReProcessing), Precision Deinterlacing(TM) , Precision Video Scaling(TM), Mosquito Noise Reduction and Picture Enhancement. The ABT2015 supports HDMI 1.3 Deep Color and is pin-out compatible with the ABT2010.

Anchor Bay used Denali's DFI-compliant PHY with their own in-house memory controller, reducing the integration effort by using this industry standardized interface. Denali's Databahn DDR PHY product offers a powerful, feature-rich technology for creating and implementing DDR PHY without the need for custom layout services. The DDR-PHY provides a configurable platform for specifying the unique functional and physical PHY characteristics for a given customer application. This specification results in a custom synthesizable design and scripts for constraints and timing validation suitable for automated place and route implementation tools.

"Consumer SoCs require specialized DDR memory systems that must address performance, quality, and time-to-market," said Mike McKeon, director, PHY Technology for Denali.