Oct. 16, 2009 (Business Wire) -- Applied Micro Circuits Corporation (NASDAQ:AMCC), or AppliedMicro, a global leader in energy conscious computing and communications solutions, today announced the first member of its APM 83K series System on Chip (SoC) family: APM 83290 - the highest performance Power Architecture^® solution available in bulk CMOS process. Designed from the ground-up to achieve industry leading speeds comparable to designs manufactured in expensive Silicon-on-Insulator processes, the APM 83290 SoC provides a level of price flexibility that makes it attractive to a wider range of systems. The APM 83290 also features proprietary PacketPro™ and MultiEase™ technologies developed from AppliedMicro’s extensive networking and processing experience for a device that delivers the best performance for wireless infrastructure, enterprise, storage, entertainment, multifunction printer and communications applications.

The APM 83290 includes a processor subsystem that integrates two Titan cores based on Power Architecture technology, delivering frequencies of 1.5 GHz per core. The Titan core is a superscalar, dual-issue, out-of-order core designed to achieve industry leading single thread performance on a per clock basis. Along with high performance, innovative circuit design techniques enable the APM 83290 to deliver speeds of 1.5 GHz in 90nm bulk CMOS while comparable designs require 45nm SOI process technology to achieve similar operating speeds. This combination of performance and price flexibility makes this solution attractive for many low cost application areas that traditionally were not serviced by Power Architecture products.

The APM 83290’s PacketPro consists of a number of acceleration blocks designed to offload the processor subsystem from commonly occurring tasks in networking applications. A fundamental component of PacketPro is a message passing architecture that simplifies data movement between the various acceleration blocks and provides Quality of Service guarantees for each flow regardless of the loading from other flows. This Quality of Service is guaranteed via a powerful and flexible Queue Manager and Traffic Manager (QMTM) block. Instead of using isolated operation offloads, the acceleration blocks are designed to offload entire protocol level tasks in order to reduce processing overhead and increase application performance. These blocks are fully software programmable in order to support proprietary features and provide upgradability for future protocol enhancements.