(Source: MARKETWIRE)
Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced
Version 5.2 of its PAC-Designer(R) mixed signal design tool suite
with new device support and productivity features. The PAC-Designer
5.2 software now supports two new higher performance Power Manager II
products: the ispPAC(R)-POWR1014-2 and ispPAC-POWR1014A-2 devices.
The POWR1014/A-2 devices are ideal for integrating Hot Swap control,
voltage rail supervision and power supply sequencing ICs.
PAC-Designer 5.2 software also supports an expanded input operating
frequency range of 40-400MHz for ispClock(TM)5400D devices and a new
graphical editor for phase and time skew programming.
Lattice Power Manager II devices integrate programmable analog and
PLD technologies to support digital power management solutions. As
more digital management functions are integrated, the verification
step in the design flow depends on robust simulation technology. The
PAC-Designer 5.2 software provides a new VHDL or Verilog HDL export
feature to extract simulation models of the embedded PLD block
featured on all Lattice Power Manager II family devices. This allows
for functional verification of sequence and supervisory logic by the
Aldec Active-HDL Lattice Web Edition simulator.
"By adding Active-HDL to the PAC-Designer software verification flow,
Lattice has provided a high-quality simulation and verification
solution for their power management product line. Logic targeted to
the PLD block of a Lattice Power Manager II family device can now be
simulated with Aldec's IEEE standard VHDL/Verilog single or mixed
language simulators," said Dave Rinehart, Vice President of
Marketing, Aldec, Inc. "As an extension to our current OEM
agreement, all Aldec simulation products, including the Active-HDL
Lattice Web Edition, now include support for the Lattice Power
Manager II family at no cost to Lattice customers."
Power Manager II devices are commonly used to integrate discrete ICs
for power management such as voltage supervisors, reset generators,
watchdog timers and Hot Swap controllers. By adding HDL export
features to PAC-Designer software, power supply sequencing, reset
signal distribution, and other digital logic integrated into a Power
Manager II device can be modeled with IEEE industry standard Verilog
HDL or VHDL. PAC-Designer and Active-HDL Lattice Web Edition
software can be downloaded for free from:
www.latticesemi.com/products/designsoftware/pacdesigner
"PAC-Designer software remains an important reason why engineers
continue to adopt Lattice power management and programmable clock
devices.
