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Xilinx Releases Pocket Power Estimator App for the iPhone

Tuesday, September 27, 2011 1:57 PM

Designers can Quickly Determine the Low Power Benefit of Xilinx's 28nm 7 Series FPGAs

SAN JOSE, Calif., Sept. 27, 2011 /PRNewswire/ -- Designers who rely on their iPhones as much as their PCs now have a quick and easy way to determine the power consumption of Xilinx's (NASDAQ: XLNX) 28nm 7 series Field Programmable Gate Arrays (FPGA). The new Pocket Power Estimator (PPE) application for Apple's iPhone enables designers to see how Xilinx's 28nm programmable platforms stack up to alternatives in delivering the lowest power consumption for their systems. Designers can download the PPE from the Apple App Store today and, for the first time ever, quickly and easily explore what-if-scenarios and get immediate feedback on the estimated power consumption compared to alternatives. For more complex and detailed power analyses, designers can use the ISE® Design Suite's XPower Estimator (XPE) and the XPower Analyzer (XPA) tools.

(Photo:  http://photos.prnewswire.com/prnh/20110927/SF75150)

(Logo:  http://photos.prnewswire.com/prnh/20020822/XLNXLOGO)

"Manufacturers of electronic systems across all our market segments are eager to either lower their current power budgets or drive higher system performance within the same power budgets," said Xilinx Distinguished Engineer and resident power 'guru' Matt Klein. "Offering the Power Pocket Estimator (PPE) on one of the most popular smartphone platforms puts power estimation in the hands of busy designers who routinely turn to their iPhone to access information, further enhancing their design productivity."

The PPE app, which can also be used with the iPad, offers an easy-to-use GUI for the quick entering of resource requirements – such as SerDes utilization, DSP, memory, logic capacity and more. Compared to the previous generation 40nm FPGAs, Xilinx 7 series FPGAs deliver about 50 percent lower total power, on average, thanks in part to the HPL (high-performance/low-power) process technology offered by foundry partner TSMC. Further components of the power envelope that drive this total power reduction include 65 percent lower maximum (worst case) static power, 25 percent lower dynamic power, 30 percent lower I/O power, and 60 percent lower transceiver power. The PPE app takes into account these aspects of total power consumption to enable designers to easily obtain a high-level estimate of power usage by functional block, and how it compares to other Xilinx or competing devices. The PPE also includes application reference examples that designers can use as starting points to customize to their own specifications.


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