Press Releases for CDNS

Press Releases
Silicon Hive Utilizes Cadence Palladium III Solution for Highest Quality IP for Multi-Core Multi-Million Gate Designs
Cadence Design Systems Appoints John Bruggeman as Chief Marketing Officer
Tilera Adopts Broad Range of Cadence Solutions for Multicore Processor Design
Cadence Low-Power Solution Selected for Global Unichip's PowerMagic Low-Power Design Methodology
BenchmarkJournal.Com Free Analyst Review for CMCSK, NVAX, ARUN, CREE, XTNT and CDNS
Nethra Enlists Cadence Incisive Palladium Accelerator/Emulator to Speed Development of Advanced HD Image Processor
UMC Adopts Cadence 40-Nanometer Reference Flow for Low Power, Verification, Implementation and DFM-Aware Design
Cadence Reports Q2 2009 Financial Results
Taiwan's Industrial Technology Research Institute Adopts Cadence C-to-Silicon Compiler to Boost Designer Productivity
Cadence Achieves First-Silicon Results on 32nm Common Platform(TM) Technology
Freescale Achieves Design Cycle Reduction and Superior Silicon Predictability With Cadence Model-Based Physical and Electrical DFM Solutions
Cadence Adds More Verification IP Products to Xuropa Labs
VeriSilicon Delivers Chip Designs on Time and at Lower Cost With Cadence InCyte Chip Estimator
Cadence Announces That STMicroelectronics Adopts Encounter Signoff Solutions for Designs From 65 to 32 Nanometers
MediaTek Deploys CoWare Solutions to Improve Product Development Cycle
Cadence Validates ARM Optimized Libraries for 45nm SOI Process
LG Electronics Adopts Cadence Conformal Technology for Improved Engineering Design Management, Faster Time to Market
TSMC and Cadence Expand Collaboration to Deliver Advanced, Feature-Rich Process Design Kits
Cadence Delivers 28-Nanometer Design Capabilities to TSMC Reference Flow 10.0
First OVM World Booth to Be Featured at Design Automation Conference in San Francisco
OVM World Collaborates on Accellera's Industry Solution for VIP Interoperability
MEDIA ADVISORY: Meet at DAC With Leading IP Suppliers During ChipEstimate.com's IP Talks!
Cadence Showcases Comprehensive Design Solutions at 46th DAC
Cadence Introduces First TLM-Driven Design and Verification Solution to Increase Engineering Productivity Over RTL-Based Flows
Cadence Announces National Semiconductor Adoption of Virtuoso Simulation Solution for Complex Analog Designs
Ricoh Joins Power Forward Initiative
Hitachi Implements 50-Million Gate Design Using Cadence Encounter Digital Implementation System
Toshiba Information Systems (Japan) Selects Cadence Mixed-Signal Design Solution
Cadence Announces Second Quarter 2009 Financial Results Webcast
STARC Integrates Cadence Encounter Solution for Complex, Large-Scale Designs
STARC Integrates Litho-Aware 45nm Design Flow Using Cadence Encounter Digital Implementation System
Fujitsu Microelectronics Solutions Adopts Cadence Verification Technology for Its Toughest Mixed-Signal Designs
Japan Aerospace Exploration Agency Adopts Cadence Virtuoso IC 6.1 and Spectre Simulator for Complex Analog and Mixed-Signal Designs
Xuropa Launches Online Lab Featuring Cadence Verification IP
Hitachi Achieves 40% Reduction in PCB Place-and-Route Design Time With Cadence Global Route Environment
Cadence Collaborates With Toshiba Corporation on Integrated Design Environment for COT and SoC Design
Cadence and Xilinx Simplify SoC Development With Enterprise Verification Capabilities for FPGA Targeted Design Platforms
CoWare, EVE Link Electronic System Virtualization, Emulation for ARM AXI-Based Systems
IP Talks! 2009: IP Returns to Center Stage at DAC
Kaben Wireless Silicon Achieves up to 7X Performance Boost With Cadence Virtuoso Accelerated Parallel Simulator
Taiwan's Industrial Technology Research Institute Achieves Digital Video Tuner Tapeout Success With Cadence Virtuoso IC 6.1
Cadence Board Member Alberto Sangiovanni-Vincentelli Honored With 2009 IEEE/RSE Wolfson James Clerk Maxwell Award
Cadence Announces Restructuring
Faraday Technology Reduces IC Power Consumption and Cuts Design Time by 20 Percent Using Cadence Low-Power Solution
Cadence QRC First Full Chip Extractor to Be Qualified for TSMC's Interoperable (iRCX) Format for 65 and 40 Nanometer Design
Casio Selects Cadence C-to-Silicon Compiler for High-Level Synthesis
Cadence Unveils Integrated Chip Planning and Implementation Solution to Improve Predictability and Reduce Risk of IC Designs
China's Academy of Sciences Adopts Cadence Incisive Xtreme III System to Validate Next-Generation Multi-Core Processor Designs
Netronome Adopts Broad Scope of Cadence Technology
Cadence Design Systems Presents at the RBC Technology, Media and Communications Conference
Cadence Senior Vice President and Chief Financial Officer Kevin Palatnik to Present at the Bank of America Merrill Lynch Technology Conference
Cadence and Virtutech Extend Metric-Driven Verification to Virtual Systems Development
Cadence Speeds Systems Development With Automated Transaction-Level Verification
Cadence Introduces Innovative FPGA-PCB Co-Design Solution
Cadence Encounter Digital IC Design Platform Adds 200 New Customers, Including Ricoh and Siano
PLDA Achieves IP Success With Cadence SuperSpeed USB (USB 3.0) Verification IP
NXP Semiconductors Accelerates Design Cycle Using New Cadence Encounter Digital Implementation System for Industry's First 45nm Digital TV Processor
Cadence and TSMC Introduce Mixed-Signal/RF Reference Design Kit in 65nm Process Technology
Cadence Announces First Quarter 2009 Financial Results Webcast
WallStSense.Com Free Research Report for Shareholders of CDNS, VMED, PMCS and RFMD
Global Unichip Announces Greater Than 3X Schedule Reduction of Full-Chip Design Closure on 50M Gate Design With New Encounter Digital Implementation System
Beacon Equity Issues Trade Alerts on Tech Stocks: ADSK, MSFT, PMTC, CDNS, VMW, MSCS
Cadence Captures EDN Innovation Award
Cadence Launches 'Industry Insights' Design Community Blog
Cadence and NEC Electronics Announce Encounter Digital Implementation System to Support NEC Electronics' System LSI With Built-In V850 CPU Core
CoWare Releases New Platform-Centric Software Analysis Tool to Increase Multicore Software Development Productivity
Cadence President and Chief Executive Officer Lip-Bu Tan to Host Annual Meeting of Stockholders
Zacks Bull & Bear of the Day Highlights: Johnson & Johnson, Cadence Design Systems, JPMorgan Chase, Bank of America and Wells Fargo
Zacks Bull and Bear of the Day Highlights: DIRECTV, Ford, Cadence Design, Synopsys and Mentor Graphics
Sequans Speeds Tapeout of 65-Nanometer Mobile WiMAX Single Die Baseband Chip With Cadence Low-Power Solution
Cadence Enhances Low-Power Solution Enabling More Predictable Power-Efficient Design
SiS Joins Power Forward Initiative to Assist in Delivering Power-Efficient Computing Platforms
Reminder - Cadence Senior Vice President and Chief Financial Officer Kevin Palatnik to Present at the Morgan Stanley Technology Conference
OVM Extended to Efficiently Manage Coverage Metrics
AMD Selects Cadence Incisive Palladium Series to Verify Complex Graphics Design
Cadence Senior Vice President and Chief Financial Officer Kevin Palatnik to Present at the Morgan Stanley Technology Conference
Adaptive Chips Adopts Cadence Incisive Verification Solution With the Open Verification Methodology (OVM)
CoWare and Rambus Announce Unique ESL Architecture Design Environment for Rambus' XDR Memory Architecture
Cadence Reports Q4 2008 Financial Results
IP Vendors to List TSMC Compatible Cores on ChipEstimate.com
Cadence ChipEstimate.com IP Ecosystem Wins 2009 DesignVision Award
New Cadence Encounter Digital Implementation System Used by STMicroelectronics for 40- and 32-Nanometer Flows
Freescale Japan Adopts Cadence Low-Power Solution to Develop Advanced Power Management Chip
Cadence Expands C-to-Silicon Compiler With High-Level Synthesis Support for Altera and Xilinx FPGAs
Ricoh Deploys CoWare ESL 2.0 Solutions for Architecture Optimization and Pre-Silicon Software Development - Jan 19 2009 10:01AM
STARC Qualifies Cadence Encounter Conformal Constraint Designer for STARCAD-CEL Flow
May Institute Launches Pediatric Specialty Center in Santa Clara County
Arasan Chip Systems Debuts Mobile Eco-System With Cadence
Cadence Low-Power Solution Enables Fujitsu Microelectronics Tapeout of 65nm WiMAX Design
Cadence Announces Fourth Quarter 2008 Financial Results Webcast
Cadence Appoints Lip-Bu Tan President and Chief Executive Officer
Hifn Selects CoWare ESL 2.0 Solutions for Design and Performance Optimization of Next-Generation Applied Services Processors - Jan 5 2009 9:59AM
Investor Alert: KGS Notifies Cadence Design Systems, Inc. Purchasers of 7 Days Until Lead Plaintiff Application Deadline in Securities Class Action Lawsuit
Cadence Unveils Next-Generation Parallel Circuit Simulator for the Verification of Complex Analog and Mixed-Signal IC Designs
Cadence Reports Q3 2008 Revenue of $232 Million and Completion of Accounting Investigation
Cadence Announces Third Quarter 2008 Financial Results Webcast - Dec 9 2008 5:28PM
ChipEstimate.com Announces New IP Partners
Cadence Introduces Industry's First Family of MIPI Standard-Compliant OVM Multi-Language Verification IP
Cadence Provides Open Source OVM Adoption Solution for VMM Users in Response to Industry Demand
Cadence Announces Encounter Digital Implementation System With EDA Industry First End-to-End Parallel Processing Flow